Intel & Micron announce “3D XPoint” memory

The magic smoke.

Moderators: phlip, Moderators General, Prelates

User avatar
Qaanol
The Cheshirest Catamount
Posts: 3035
Joined: Sat May 09, 2009 11:55 pm UTC

Intel & Micron announce “3D XPoint” memory

Postby Qaanol » Tue Jul 28, 2015 9:56 pm UTC

Intel and Micron just announced a new form of non-volatile memory called “3D XPoint” (pronounced “cross-point”), which they claim “is up to 1,000 times faster and has up to 1,000 times greater endurance than NAND, and is 10 times denser than conventional memory.”

The BBC article about this development describes the memory cells as storing bits by altering the resistance of the material itself, but all I see on the Intel page is that they “invented unique material compounds and a cross point architecture”.

So, any thoughts on how exactly this works? It doesn’t quite sound like memristors, but maybe something similar?
wee free kings

User avatar
PeteP
What the peck?
Posts: 1451
Joined: Tue Aug 23, 2011 4:51 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby PeteP » Tue Jul 28, 2015 10:11 pm UTC

I just wanted to say: Wow. If these numbers are accurate that is a giant step for a significant bottleneck. Though I assume at least in the beginning the price tag will be quite high too.

User avatar
Flumble
Yes Man
Posts: 1944
Joined: Sun Aug 05, 2012 9:35 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby Flumble » Wed Jul 29, 2015 12:31 am UTC

Qaanol wrote:“3D XPoint” (pronounced “cross-point”)

I'm going to call it ex-point until the day they rename it to cross-point (read: forever). It's like the sms-generation has taken over the marketing industry. :x

So after a bit of reading, it's not DRAM, it's not SRAM, it's not NAND, it's not PCM, it's most probably not memristors (because HP has patents on that). And looking at the diagram, it's unclear to me if you can read/write a whole row at a time or if it's single addressing all the time.

What we "really need" to take a leap forward in computing, is distributed (RISC) cores tucked away between swathes of (non-volatile) memory, connected to each other with wide buses. And 3D chips of course, but let's start with the easier problem.

User avatar
Qaanol
The Cheshirest Catamount
Posts: 3035
Joined: Sat May 09, 2009 11:55 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby Qaanol » Wed Jul 29, 2015 3:37 am UTC

Having now read several more articles on the matter, concrete info is still pretty scarce. I’ve gathered that Intel, Micron, and their IMFT partnership will each produce 3D XPoint memory, they are aiming to release enterprise-class products in 2016, and “the price will fall between DRAM and NAND” according to Tom’s hardware.

It’s also worth noting that “1,000 times faster than NAND” means it will be approximately as fast as DRAM, or a little bit slower. Similarly, “10 times denser than conventional memory” puts it at about the same density as NAND flash. And of course “non-volatile” could mean the values last anywhere from just a few days to arbitrarily many years. Also, “1,000 times greater endurance than NAND” is fantastic if it’s aiming to replace (or supplement) permanent storage, but totally insufficient if it’s supposed to unseat DRAM.

So we really don’t know much of anything about this new technology yet, except that each bit can be toggled individually, and it’s fast. Depending on the specifics, it could turn out to be a replacement for SSDs, or a replacement for RAM, or both, or an additional cache-style intermediate level of storage.
wee free kings

User avatar
Qaanol
The Cheshirest Catamount
Posts: 3035
Joined: Sat May 09, 2009 11:55 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby Qaanol » Mon Aug 17, 2015 5:56 pm UTC

I just came across this PDF from 2011 which is a slide deck about something called “CMOx Cross-point Memory” by a company named Unity which was backed by Seagate and Micron. It describes a cross-point style replacement for DRAM that functions by modulating the level of oxygen in thin films of metal. The illustrations are very similar to the recently-announced 3D XPoint, right down to the presence of a “selector” layer within each cell.

The slides have a little more detail than what Intel and Micron announced, but not a whole lot. For instance, the layers of the cells are labels as TE, IMO, CMO, and BE. I have heard that Intel bought Unity in 2011, so 3D XPoint seems likely to be a refinement of CMOx Cross-point. Of course four years is a lot of time, and there may have been substantial changes to the design since then, but it’s something.
wee free kings

User avatar
david.windsor
Posts: 121
Joined: Mon Sep 09, 2013 3:08 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby david.windsor » Fri Aug 28, 2015 6:15 pm UTC

Qaanol wrote:
So we really don’t know much of anything about this new technology yet, except that each bit can be toggled individually, and it’s fast. Depending on the specifics, it could turn out to be a replacement for SSDs, or a replacement for RAM, or both, or an additional cache-style intermediate level of storage.


I got the impression this was aimed at the storage market
"All those ... moments, will be lost ... in time, like tears ... in rain."

wumpus
Posts: 494
Joined: Thu Feb 21, 2008 12:16 am UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby wumpus » Mon Aug 31, 2015 2:41 pm UTC

david.windsor wrote:I got the impression this was aimed at the storage market

Everything anounced is aimed at the storage market.

Best guess is that it is a drop in replacement for a [pci-e]SSD. It is far too slow to simply place on a DRAM stick (and presumably the interfaces wouldn't be close), but that doesn't mean that you can't use the stuff as virtual-ram/last level cache. I suspect that there will be plenty of uses of the stuff as virtual ram in servers when first released.

My first impressions of the stuff is that it should be able to replace a large amount of DRAM in the system (I ran a system with 4G until quite recently and barely noticed an issue) as well as make the speed of flash-storage more or less moot (acting as a cache for SSDs). Of course, if this is against Intel and Microns' interest, this might take awhile: this makes how the Intel/Micron 3d flash memory (a completely different system based on traditional flash) is used. As far as I know, Samsung lets the controller use a "well" of ~32 bits as a single bit. This bumps speed and resilience to near single-bit levels. If Intel/Micron's 3d-flash system doesn't work like this [or at least very well] you could find a lot of motherboards on the market with fairly large levels of 3d xpoint vram/cache that would marginalize the difference between premium and bulk SSDs.

I'd also have to wonder how many mobile devices would love to be able to shut down DRAM at whim (or at least cut way down on needed DRAM). Using DRAM as a write-through cache to xpoint would mean they could pretty much shut things down with only the issue of slowly getting back up to speed (and slogging along at low speeds without DRAM for background jobs).

User avatar
Qaanol
The Cheshirest Catamount
Posts: 3035
Joined: Sat May 09, 2009 11:55 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby Qaanol » Sat Oct 03, 2015 2:56 pm UTC

I just found this whitepaper (PDF) about the Cross-point Array technology on the old Unity Semiconductor website, via the Wayback Machine. I haven’t read the whole thing yet, but it appears to give some insight into the design of the crisscrossing array, much as the previously-linked PDF gave insight into the design of the memory cells themselves.

Here is a list of Unity Semiconductor’s patents through 2012:
Spoiler:
Patent # Issue Date Title
US 6,753,561 22-Jun-04 Cross Point Memory Array Using Multiple Thin Films
US 6,798,685 28-Sep-04 Multi-Output Multiplexor
US 6,831,854 14-Dec-04 Cross Point Memory Array Using Distinct Voltages
US 6,834,008 21-Dec-04 Cross Point Memory Array Using Multiple Modes Of Operation
US 6,836,421 28-Dec-04 Line Drivers That Fits Within A Specified Line Pitch
US 6,850,429 1-Feb-05 Cross Point Memory Array With Memory Plugs Exhibiting A Characteristic Hysteresis
US 6,850,455 1-Feb-05 Multiplexor Having A Reference Voltage On Unselected Lines
US 6,856,536 15-Feb-05 Non Volatile Memory With A Single Transistor And Resistive Memory Element
US 6,859,382 22-Feb-05 Memory Array Of A Non-Volatile RAM
US 6,870,755 22-Mar-05 Rewritable Memory With Non-Linear Memory Element
US 6,906,939 14-Jun-05 Re-Writable Memory With Multiple Memory Layers
US 6,909,632 21-Jun-05 Multiple Modes Of Operation In A Cross Point Array
US 6,917,539 12-Jul-05 High Density NVRAM
US 6,940,744 6-Sep-05 An Adaptive Programming Technique For A Re-Writable Conductive Memory Device
US 6,965,137 15-Nov-05 Multi-Layer Conductive Memory Device
US 6,970,375 29-Nov-05 Providing A Reference Voltage To A Cross Point Memory Array
US 6,972,985 6-Dec-05 Memory Element Having Islands
US 6,992,922 31-Jan-06 Cross Point Memory Array With Memory Plugs Exhibiting A Characteristic Hysteresis
US 7,009,235 7-Mar-06 Conductive Memory Stack With Non-Uniform Width
US 7,009,909 7-Mar-06 Line Drivers That Use Minimal Metal Layers
US 7,020,006 28-Mar-06 Discharge Of Conductive Array Lines In Fast Memory
US 7,020,012 28-Mar-06 Cross Point Memory Array Using Distinct Voltages
US 7,038,935 2-May-06 A 2-Terminal Trapped Charge Memory Device With Voltage Switchable Multi-Level Resistance
US 7,042,035 9-May-06 Memory Array With High Temperature Wiring
US 7,054,183 30-May-06 An Adaptive Programming Technique For A Re-Writable Conductive Memory Device
US 7,057,914 6-Jun-06 Cross Point Memory Array With Fast Access Time
US 7,063,984 20-Jun-06 Low Temperature Deposition Of Complex Metal Oxide (CMO) Memory Materials For Non-Volatile Memory Integrated Circuits
US 7,067,862 27-Jun-06 Conductive Memory Device With Conductive Oxide Electrodes
US 7,071,008 4-Jul-06 Multi-Resistive State Material That Uses Dopants
US 7,075,817 11-Jul-06 Two Terminal Memory Array Having Reference Cells
US 7,079,442 18-Jul-06 Layout Of Driver Sets In Cross Point Memory Array
US 7,082,052 25-Jul-06 Multi-Resistive State Element With Reactive Metal
US 7,095,643 22-Aug-06 Re-Writable Memory With Multiple Memory Layers
US 7,095,644 22-Aug-06 Conductive Memory Array Having Page Mode And Burst Mode Read Capability
US 7,099,179 29-Aug-06 Conductive Memory Array Having Page Mode And Burst Mode Write Capability
US 7,126,841 24-Oct-06 Non Volatile Memory With A Single Transistor And Resistive Memory Element
US 7,149,107 12-Dec-06 Providing A Reference Voltage To A Cross Point Memory Array
US 7,149,108 12-Dec-06 Memory Array Of A Non-Volatile RAM
US 7,158,397 2-Jan-07 Line Drivers That Fits Within A Specified Line Pitch
US 7,180,772 20-Feb-07 High-Density NVRAM
US 7,186,569 6-Mar-07 Conductive Memory Stack With Sidewall
US 7,227,767 5-Jun-07 Cross Point Memory Array With Fast Access Time
US 7,227,775 5-Jun-07 Two Terminal Memory Array Having Reference Cells
US 7,309,616 18-Dec-07 Laser Annealing Of Complex Metal Oxides (CMO) Memory Materials For Non-Volatile Memory Integrated Circuits
US 7,326,979 5-Feb-08 Resistive Memory Device With A Treated Interface
US 7,327,600 5-Feb-08 Storage Controller For Multiple Configurations Of Vertical Memory
US 7,327,601 5-Feb-08 Providing A Reference Voltage To A Cross Point Memory Array
US 7,330,370 12-Feb-08 Enhanced Functionality In A Two Terminal Memory Array
US 7,372,753 13-May-08 Two-Cycle Sensing In A Two-Terminal Memory Array Having Leakage Current
US 7,379,364 27-May-08 Sensing A Signal In A Two-Terminal Memory Array Having Leakage Current
US 7,382,644 3-Jun-08 Two Terminal Memory Array Having Reference Cells
US 7,382,645 3-Jun-08 Two Terminal Memory Array Having Reference Cells
US 7,394,679 1-Jul-08 Multi-Resistive State Element With Reactive Metal
US 7,400,006 15-Jul-08 Conductive Memory Device With Conductive Oxide Electrodes
US 7,436,723 14-Oct-08 Method For Two-Cycle Sensing In A Two-Terminal Memory Array Having Leakage Current
US 7,439,082 21-Oct-08 Conductive Memory Stack With Non-Uniform Width
US 7,457,147 25-Nov-08 Two Terminal Memory Array Having Reference Cells
US 7,505,347 17-Mar-09 Method For Sensing A Signal In A Two-Terminal Memory Array Having Leakage Current
US 7,522,468 21-Apr-09 Serial Memory Interface
US 7,528,405 5-May-09 Conductive Memory Stack With Sidewall
US 7,538,338 26-May-09 Memory Using Variable Tunnel Barrier Widths
US 7,539,811 26-May-09 Scaleable Memory Systems Using Third Dimension Memory
US 7,593,284 22-Sep-09 Memory Emulation Using Resistivity-Sensitive Memory
US 7,618,894 17-Nov-09 Multi-Step Selective Etching For Cross-Point Memory
US 7,619,945 17-Nov-09 Memory Power Management
US 7,633,789 15-Dec-09 Planar Third Dimensional Memory With Multi-Port Access
US 7,633,790 15-Dec-09 Multi-Resistive State Memory Device With Conductive Oxide Electrodes
US 7,649,788 19-Jan-10 Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits
US 7,652,501 26-Jan-10 Programmable Logic Device Structure Using Third Dimensional Memory
US 7,652,502 26-Jan-10 Field Programmable Gate Arrays Using Resistivity Sensitive Memories
US 7,701,791 20-Apr-10 Low Read Current Architecture For Memory
US 7,701,834 20-Apr-10 Movable Terminal In A Two Terminal Memory Array
US 7,715,244 11-May-10 Non-Volatile Register Having A Memory Element And Register Logic Vertically Configured On A Substrate
US 7,715,250 11-May-10 Circuitry And Method For Indicating A Memory
US 7,719,876 18-May-10 Preservation Circuit And Methods To Maintain Values Representing Data In One Or More Layers Of Memory
US 7,742,323 22-Jun-10 Continuous Plane Of Thin-Film Materials For A Two-Terminal Cross-Point Memory
DE FR NL 1743340 23-Jun-10 Non-Volatile Programmable Memory
US 7,747,817 29-Jun-10 Performing Data Operations Using Non-Volatile Third Dimension Memory
US 7,751,221 6-Jul-10 Media Player With Non-Volatile Memory
US 7,765,380 27-Jul-10 Fast Data Access Through Page Manipulation
US 7,796,451 14-Sep-10 Integrated Circuits And Methods To Compensate For Defective Memory In Multiple Layers Of Memory
US 7,808,809 5-Oct-10 Transient Storage Device Emulation Using Resistivity-Sensitive Memory
US 7,813,210 12-Oct-10 Multiple Type Memory
US 7,818,523 19-Oct-10 Securing Data In Memory Device
US 7,822,913 26-Oct-10 Emulation Of A NAND Memory System
US 7,830,701 9-Nov-10 Contemporaneous Margin Verification And Memory Access For Memory Cells In Cross Point Memory Arrays
US 7,832,090 16-Nov-10 Method Of Making A Planar Electrode
US 7,834,660 16-Nov-10 State Machines Using Resistivity-Sensitive Memories
US 7,836,273 16-Nov-10 Fast Data Access Through Page Manipulation
US 7,839,702 23-Nov-10 Three-Dimensional Non-Volatile Register With An Oxygen-Ion-Based Memory Element And A Vertically-Stacked Register Logic
US 7,847,330 7-Dec-10 Four Vertically Stacked Memory Layers In A Non-Volatile Re-Writeable Memory Device
US 7,870,333 11-Jan-11 Performing Data Operations Using Non-Volatile Third Dimension Memory
US 7,876,594 25-Jan-11 Memory Emulation Using Resistivity-Sensitive Memory
US 7,877,541 25-Jan-11 Method And System For Accessing Non-Volatile Memory
US 7,884,349 8-Feb-11 Selection Device For Re-Writable Memory
US 7,888,711 15-Feb-11 Continuous Plane Of Thin-Film Materials For A Two-Terminal Cross-Point Memory
US 7,889,539 15-Feb-11 Multi-Resistive State Memory Device With Conductive Oxide Electrodes
US 7,889,571 15-Feb-11 Buffering Systems Methods For Accessing Multiple Layers Of Memory In Integrated Circuits
US 7,889,591 15-Feb-11 ASIC Including Vertically Stacked Embedded Non-Flash Re-Writable Non-Volatile Memory
US 7,897,951 1-Mar-11 Continuous Plane Of Thin-Film Materials For A Two-Terminal Cross-Point Memory
US 7,898,841 1-Mar-11 Preservation Circuit And Methods To Maintain Values Representing Data In One Or More Layers Of Memory
US 7,902,868 8-Mar-11 Field Programmable Gate Arrays Using Resistivity Sensitive Memories
US 7,903,485 8-Mar-11 Integrated Circuits And Methods To Compensate For Defective Non-Volatile Embedded Memory In One Or More Layers Of Vertically Stacked Non-Volatile Embedded Memory
US 7,913,049 22-Mar-11 Securing Non-Volatile Data In An Embedded Memory Device
US 7,917,691 29-Mar-11 Memory Device With Vertically Embedded Non-Flash Non-Volatile Memory For Emulation Of NAND Flash Memory
US 7,961,510 14-Jun-11 Integrated Circuits To Control Access To Multiple Layers Of Memory In A Solid State Drive
US 7,961,527 14-Jun-11 Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits
US 7,961,529 14-Jun-11 Processor Including Vertically Stacked Third-Dimensional Embedded Re-Writeable Non-Volatile Memory And Registers
US 7,978,501 12-Jul-11 Method For Contemporaneous Margin Verification And Memory Access For Memory Cells In Cross-Point Memory Arrays
US 7,985,963 26-Jul-11 Memory Using Variable Tunnel Barrier Widths
US 7,986,567 26-Jul-11 Read Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits
US 7,990,762 2-Aug-11 Integrated Circuits To Control Access To Multiple Layers Of Memory
US 7,995,371 9-Aug-11 Threshold Device For A Memory Array
US 7,996,600 9-Aug-11 Memory Emulation In An Electronic Organizer
US 7,999,571 16-Aug-11 State Machines Using Non-Volatile Re-Writeable Two-Terminal Resistivity-Sensitive Memories
US 8,000,121 16-Aug-11 Solid State Drive With Non-Volatile Memory For A Media Device
US 8,000,122 16-Aug-11 Media Player With Non-Volatile Memory
US 8,000,138 16-Aug-11 Scaleable Memory Systems Using Third Dimension Memory
US 8,003,511 23-Aug-11 Memory Cell Formation Using Ion Implant Isolated Conductive Metal Oxide
US 8,004,309 23-Aug-11 Programmable Logic Device Structure Using Third Dimensional Memory
US 8,018,790 13-Sep-11 Serial Memory Interface
US 8,020,132 13-Sep-11 Combined Memories In Integrated Circuits
US 8,027,215 27-Sep-11 Array Operation Using A Schottky Diode As A Non-Ohmic Isolation Device
US 8,031,509 4-Oct-11 Conductive Metal Oxide Structures In Non-Volatile Re-Writable Memory Devices
US 9,031,545 4-Oct-11 Low Read Current Architecture For Memory
US 8,031,510 4-Oct-11 Ion Barrier Cap
US 8,032,692 4-Oct-11 System For Accessing Non-Volatile Memory

This page talks a little bit about the CMOx memory cells, though without great detail:
Spoiler:
CMOx™ Device

The memory effect of CMOx™ is created by moving Oxygen ions between two metal oxides under electric field.

CMOx™ is powered by the physics of Oxygen vacancy movement, which is entirely different from the physics of electrons that makes NAND work.
CMOx™ is a two layer structure comprised of a conductive metal oxide (CMO) and a second insulating metal oxide (IMO).
The CMO and IMO each have crystal structures conducive to the trapping and releasing of Oxygen ions.
The CMO is an ionic conductor and electronic conductor.
The IMO is an ionic conductor and electronic insulator.
During the fabrication of CMOx™, the metals ratio within the IMO and CMO are adjusted to optimize the CMOx™ memory cell’s characteristics.

The CMOx™ memory cell is a two terminal device: the IMO and CMO are fabricated between two electrodes (top and bottom). By way of contrast, the NAND memory cell is a three terminal device: source, drain and gate.

In the erased state, Oxygen ions are concentrated in the CMO.

When an electric field is applied from the direction of the CMO towards the IMO, the Oxygen ions move to the IMO. The increased concentration of Oxygen ions in the IMO increases the resistivity of the IMO. Unity’s design IP includes sensing algorithms and sensing circuitry to detect the changes in the electrical properties of the CMO and IMO. Thus the current through the selected cell are compared versus a reference to detect this programmed state of the CMOx™.

When an electric field is applied from the direction of the IMO to the CMO, the Oxygen ions move back to the CMO. The decreased Oxygen ion concentration in the IMO decreases the resistivity of the IMO. Unity then compares the current through the selected cell with a reference as described above.

Unity has demonstrated tens of thousands of cycles through CMOx™ cells.

By using a specific electric field, Unity can change the location of ions and thereby precisely set the cell current. This precise cell current tuning enables multi-level cell architecture.

Simple geometry, simple device physics.
No forming, not filamentary.
Currents defined by geometry of the device (IMO thickness and area).
Uniform conduction and area scaling of program, erase, and read current.
Full control over currents by controlling the electric field.

More interestingly, here are their technical papers:
Spoiler:
CMOxTM, 3D Cross-point and Terabit Memories
Christophe Chevallier
Unity Semiconductor Corporation

Why CMOxTM Cross Point Memory Arrays?
Bruce Bateman
Unity Semiconductor Corporation

New CMOx™ Cross-Point Memory Technology Based on a Novel Oxide Memory Element
John Sanchez, Jr., PhD, Rene Myer, PhD., Wayne Kinney, PhD., et. al.
Unity Semiconductor Corporation

A 0.13 μm 64Mb Multi-Layered Conductive Metal-Oxide Memory
Christophe Chevallier, Chang Siau, Dennis Lim, Sri Namala, Misako Matsuoka, Bruce Bateman, Darrell Rinerson
Unity Semiconductor Corporation

Oxide Dual-Layer Memory Element for Scalable Non-Volatile Cross-Point Memory Technology
Rene Meyer, PhD., Lawrence Schloss, PhD., Julie Brewer, Roy Lambertson, Wayne Kinney, PhD., John Sanchez, PhD., and Darrell Rinerson
Unity Semiconductor Corporation

And here are their press releases including one about their partnership with Micron.
wee free kings

User avatar
Copper Bezel
Posts: 2416
Joined: Wed Oct 12, 2011 6:35 am UTC
Location: Web exclusive!

Re: Intel & Micron announce “3D XPoint” memory

Postby Copper Bezel » Sat Mar 26, 2016 10:04 pm UTC

I like that it's definitely not a memristor, and definitely not what HP calls a memristor, but still closer to what HP calls a memristor than an actual memristor would be to either of them.
So much depends upon a red wheel barrow (>= XXII) but it is not going to be installed.

she / her / her

User avatar
mosc
Doesn't care what you think.
Posts: 5370
Joined: Fri May 11, 2007 3:03 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby mosc » Thu Aug 11, 2016 4:47 pm UTC

Actual demo products exist now:
http://www.tomshardware.com/news/intel- ... 32434.html
Targetting 2017 sales.

Seems clear this tech needs to get off the PCI bus and onto a memory controller. It's looking like a much larger memory pool that's a little slower. No more paging and virtual memory.
Title: It was given by the XKCD moderators to me because they didn't care what I thought (I made some rantings, etc). I care what YOU think, the joke is forums.xkcd doesn't care what I think.

KnightExemplar
Posts: 5489
Joined: Sun Dec 26, 2010 1:58 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby KnightExemplar » Thu Aug 11, 2016 9:12 pm UTC

Impressive tech, but this worries me: http://media.bestofmicro.com/1/H/602693/original/03.jpg

DRAM isn't exactly dense. We're looking at tens, or low-hundreds of GB of storage. Not at the 100TBs that was just announced by Toshiba by classic Flash RAM.

Less dense (and therefore more expensive) than Flash, while being much much faster than it, creates an awkward zone. Big Data customers have DRAM-only databases, but such databases / storage is simply outside the price point of a standard consumer. Hell, how many people actually use say... 2TB of DDR3 or DDR4?
First Strike +1/+1 and Indestructible.

wumpus
Posts: 494
Joined: Thu Feb 21, 2008 12:16 am UTC

Some competition

Postby wumpus » Tue Sep 06, 2016 7:19 pm UTC

http://nantero.com/technology/

No idea how close they are to production, but they inked a deal with fujitsu recently. Pretty much claim the same or more as 3d Xpoint, but there seem to be the slightest whiff of wesealing that makes me think that you can have:
speed of RAM OR less power than flash OR higher density than flash
Still, there have always been various sorts of next generation memories steamrollered by Moore's law. Note that Moore's law is still viable in memory (and stacked 3d transistors *count*, the paper merely was about transistors per die), so these things have to be wildly easier to manufacture than current storage schemes to survive in tomorrow's market.

Note that one of the reasons Intel (and even more expensive iron from IBM) seems to have the server market sewn up is that the cost of the memory per server is astronomical. It doesn't make sense to have a less powerful server no matter how much cheaper if it doesn't get good returns for the cost of the memory. Switch to "3d xpoint", NRAM, or even SLC flash and suddenly the whole game might change. Considering AMD has already shown a relatively low power/massive bandwidth to a 4G memory (a mere cache for a good-sized server), they might manage to create a cost effective server by using such things as "main memory". I'm wondering when somebody will try it (preferably at the MMU level, Intel has a bunch of slides that merely imply using regular old flash across a PCIe link. This is the slow & steady progress of somebody who wants to milk all the money out of each stage and not hungry for a disruption).

User avatar
mosc
Doesn't care what you think.
Posts: 5370
Joined: Fri May 11, 2007 3:03 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby mosc » Fri Sep 30, 2016 1:48 pm UTC

I think, in short, system memory's latency is getting too long and it will move on-dye. 3D XPoint (or some other branding, what's in a name?) will become the system memory and be much larger than today. Disks will essentially be repalced by network storage since the system memory is no-volatile even start-up information is not needed. Anything archival will not be purely local. Flash will dominate storage servers where volume is key.
Title: It was given by the XKCD moderators to me because they didn't care what I thought (I made some rantings, etc). I care what YOU think, the joke is forums.xkcd doesn't care what I think.

KnightExemplar
Posts: 5489
Joined: Sun Dec 26, 2010 1:58 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby KnightExemplar » Fri Sep 30, 2016 9:45 pm UTC

mosc wrote:I think, in short, system memory's latency is getting too long and it will move on-dye. 3D XPoint (or some other branding, what's in a name?) will become the system memory and be much larger than today. Disks will essentially be repalced by network storage since the system memory is no-volatile even start-up information is not needed. Anything archival will not be purely local. Flash will dominate storage servers where volume is key.


I disagree. DRAM is still faster than 3D XPoint and Hard Drives have significantly higher bandwidth than standard networking technologies.

http://www.legitreviews.com/wp-content/ ... chmark.jpg

Don't get me wrong, 2GB/s is mighty fast, but DDR3 RAM is ~20GB/s. Transitioning from RAM to Optane is going to slow down virtually everybody. Optane seems like a (potential) future of NAND Flash, but Intel needs to get the costs down.

MLC and TLC SSDs have proven that no one cares about speed anymore of storage. SSDs have only gotten slower (how many of us are actually buying the Intel 750 PCIe 2GB/s drive for $750. Anybody??). Instead, people are buying slower and slower drives, like the Samsung 850 Evo (TLC, so its significantly slower than normal MLC drives). In fact, we can go back to SLC SSDs if anyone actually cared about speed.

----------

Another note: modern Hard Drives have a bandwidth of ~150MB/s (at least, mine does, last time I benchmarked it). Networks are practically capped at 1gbps (Ethernet) or 1.2gbps (802.11 ac under perfect conditions). There's a big difference between 1gbps and 10gbps costwise, so in practice, Hard Drives are much faster than any networking technology.

The new memory tiers, when Optane becomes big, will be:

* Registers (immediate access by CPU, as they're inside the cores)
* L1 / L2 / L3 Cache
* DDR4 RAM (~20GB/s for Dual-channel systems)
* Optane (~2GB/s)
* PCIe SSDs (~1.8GB/s) (Including M.2 PCIe or SATAe SSDs)
* SATA3 MLC SSDs (~500MB/s)
* SATA3 TLC "cheap" SSDs (~300MB/s)
* LTO-7 Tape Drives (300MB/s... yeah... really. The latency is killer though and the drives are expensive)
* Hard Drives (~150MB/s)
* Networks (~100MB/s) (Assuming 1gbps Ethernet)
* Lol BluRay (~15MB/s)

The above numbers are bandwidth, not latency. Latency seems to be a bigger draw for Optane. I'm not sure if Optane is going to be a "revolution", based on the relatively slow adoption of PCIe SSDs.
First Strike +1/+1 and Indestructible.

korona
Posts: 495
Joined: Sun Jul 04, 2010 8:40 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby korona » Thu Oct 06, 2016 6:35 pm UTC

mosc wrote:I think, in short, system memory's latency is getting too long and it will move on-dye. 3D XPoint (or some other branding, what's in a name?) will become the system memory and be much larger than today. Disks will essentially be repalced by network storage since the system memory is no-volatile even start-up information is not needed. Anything archival will not be purely local. Flash will dominate storage servers where volume is key.

Today's memory is physically too large to be moved onto the die. I also doubt that system memory will be replaced by NVRAM anytime soon. NVRAM may be a good replacement for disk storage but main RAM does not only require high bandwidth but also (and probably more importantly, depending on the work load) low latency. It is relatively easy to get high bandwidth through parallelization (e.g. RAID; PCIe can sustain about 15 GB/s using 16 lanes) but improving latency requires fundamental technology improvements.

EDIT: It seems that the first generation of 3D XPoint will achieve a latency of 9 microseconds. DRAM latency is in the 100 ns range.

KnightExemplar
Posts: 5489
Joined: Sun Dec 26, 2010 1:58 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby KnightExemplar » Thu Oct 06, 2016 6:43 pm UTC

korona wrote:
mosc wrote:I think, in short, system memory's latency is getting too long and it will move on-dye. 3D XPoint (or some other branding, what's in a name?) will become the system memory and be much larger than today. Disks will essentially be repalced by network storage since the system memory is no-volatile even start-up information is not needed. Anything archival will not be purely local. Flash will dominate storage servers where volume is key.

Today's memory is physically too large to be moved onto the die. I also doubt that system memory will be replaced by NVRAM anytime soon. NVRAM may be a good replacement for disk storage but main RAM does not only require high bandwidth but also (and probably more importantly, depending on the work load) low latency. It is relatively easy to get high bandwidth through parallelization (e.g. RAID; PCIe can sustain about 15 GB/s using 16 lanes) but improving latency requires fundamental technology improvements.


And don't forget, memory is moving forward as well. HBM is the future.

Image

Image

Not quite "on die", but "on package" (so its literally inside the chip, but the chip itself is starting to become a system). AMD's Fury X has a 4096-lane bus between the GPU and the HBM memory.

-----------

Intel "Crystalwell" also accomplished this, through different means.

Image

See that big chunk of RAM next to the die? They're all on the chip now.

-----------------

Crystalwell == ~128MB. AMD Fury X is 4GB of RAM. This stuff is cutting-edge, so they're still smaller than standard DDR4 sticks. The HBM memory, despite being "wide as fuck" (4096? holy shit) is downclocked due to heating issues at the moment. (In contrast, each DDR4 stick have 288 lines of copper on them. Even 8 DDR4 sticks is only 2304 lines of copper)

So yeah, its technology that's just barely possible and not quite cost-effective yet. But its clearly where the big-players are going. Maybe in 10 years we won't be buying DDR-sticks anymore, as the RAM will be on-chip (but not on-die). There's just no way to run 4096 lines of copper on a motherboard. Plus, being so physically close to the CPU / GPU means that latency will improve. (Something about the speed of light. You know... light can only travel ~1cm per clock-tick right? 300 million meters/second isn't very fast when the clock-speeds are pushing 3-billion ticks per second)
First Strike +1/+1 and Indestructible.

korona
Posts: 495
Joined: Sun Jul 04, 2010 8:40 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby korona » Thu Oct 06, 2016 8:45 pm UTC

Yes, high bandwidth definitely makes sense for stuff like GPUs with a uniform access pattern (stuff like primitive buffers are usually accessed sequentially).

It does not help so much with the random access patterns of most CPU-bound code. However moving stuff like memory or PCI lanes closer to the CPU will help improving latency even for CPU-bound tasks. This is not really a new idea: Historically CPUs (in the ICH era) had an external memory controller whereas today's CPU integrate the memory controller and PCIe root complex with the CPU. However I don't know how much of the memory latency is caused by the wire though; I guess most of it is caused by stuff like DRAM access times and coherency protocols.

I could imagine that stuff like heat dissipation could be a problem for current technologies (this is anecdotally: my CPU and memory each have their own heatsinks; pairing them together would probably require much more effective cooling) but it I guess we will see more such solutions in the future.

User avatar
mosc
Doesn't care what you think.
Posts: 5370
Joined: Fri May 11, 2007 3:03 pm UTC

Re: Intel & Micron announce “3D XPoint” memory

Postby mosc » Mon Oct 10, 2016 12:00 pm UTC

Well I also think the size of DRAM isn't needed when you have an XPoint-like "dimm" a few inches away either. These multi-layer memory technologies will eventually lead to much denser DRAM as well. I'm thinking more of additional layers on top of the CPU die for "memory". Imagine a system today with a 1GB GDDR5 on die memory layer that's 512-bit wide. It's not very big and it's volatile but it's extremely fast. The memory controller is no longer interfacing through the motherboard at all (hence the width). 16 PCI lanes then support a very fast piece of this "XPoint" drive that sits on a DIMM on the motherboard. It's 1TB or so lets say and not much slower than DDR3. The computer also has plenty of network storage that can keep up with 1gb/s sufficient for 4K video or other streaming needs.
Title: It was given by the XKCD moderators to me because they didn't care what I thought (I made some rantings, etc). I care what YOU think, the joke is forums.xkcd doesn't care what I think.


Return to “Hardware”

Who is online

Users browsing this forum: No registered users and 3 guests